1. Field of the Invention
The present invention generally relates to the detection of erroneous data bits and, more particularly, to the extension of the error detection capability of a given code without extension of the number of coded bits required.
2. Description of the Prior Art
Special coding techniques are well known for the detection and correction of erroneous bits of data words read from computer memories. Depending upon the number of check bits and the complexity of the coding employed, multiple bit errors can be detected and corrected. As might be expected, the fewer the bits being examined and processed for detection and correction of errors, the simpler the required hardware/software to do the job.
Occasionally, it is possible to extend the capability of a given technique to detect and/or correct faulty data bits by the addition of relatively modest means to the existing structure. One such example is described in the IBM.RTM. Technical Disclosure bulletin article by B. C. Bachman et al., entitled "Multiple Error Correction", Vol. 13, No. 8, January 1971, page 2190. In that instance, a log is maintained of known double errors in terms of the addresses of the words in which they occur. Each time that such words are addressed, the known faulty bits are simply inverted upon read out. The normal and more complex procedure of complement/recomplement to correct double faults is averted and system performance is enhanced. However, no extension of error detection capability is achieved.
The complement/recomplement procedure utilizes a single error correction-double error detection (SEC/DED) code such as described in U.S. Pat. No. 3,601,798 issued on Aug. 24, 1971 to Hsiao and assigned to the present assignee. When a double error is detected, the word fetched from memory is read into a register and the complement of the fetched word is rewritten back into the original memory location. A fetch cycle is then executed on the complement of the fetched word and the word and its complement are compared in an Exclusive OR circuit that identifies the location of the failing bits. This information is utilized to complement the incorrect bits in the original fetched word.
U.S. Pat. Nos. 3,656,107, issued on Apr. 11, 1972 to Hsiao et al., and 3,685,014, issued on Aug. 15, 1972 to Hsiao et al., both assigned to the present assignee, show methods for detecting and correcting double errors and for detecting triple errors (DEC/TED) but those methods utilize more check bits than do basic SEC/DEC schemes. The same is true of U.S. Pat. No. 3,714,629, issued on Jan. 30, 1973 to Hong et al., and assigned to the present assignee.